Category Trusted Electronics

Fault Attacks on ECC Signature Verification

Digital signatures used in embedded systems are often based on elliptic curve cryptography (ECC) thanks to its performance and low memory profile. In secure boot processes they provide the cryptographic foundation for guaranteeing the authenticity of a firmware image. At the same time, these resource-constraints and the physical exposure of such devices makes them prime targets for fault attacks. Prior work studied faults on signature generation in depth, yet nobody had systematically asked how vulnerable signature verification is to fault attacks combined with carefully crafted signature inputs. That is exactly the gap we set out to close.

Fraunhofer AISEC commissioned by the German Federal Office for Information Security (BSI): New study on the synthesis of cryptographic hardware implementations

The study by Fraunhofer AISEC on the security of cryptographic hardware implementations focuses on physical attacks on hardware, such as side-channel attacks and fault attacks, as well as measures to defend against them. These protective mechanisms can potentially be compromised by optimizations in the chip design process. The study shows that protective measures should be integrated into complex design processes and taken into account in hardware design synthesis in order to be resilient to hardware attacks. The findings will help hardware designers to develop robust and secure chips.

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