Tag Hardware Security

Laboratory Security Evaluation of the OpenTitan Silicon Root of Trust

This post summarizes a joint hardware security evaluation of OpenTitan® engineering and production silicon by Fraunhofer AISEC in cooperation with design teams from Google, lowRISC® and Nuvoton.
The goal was to validate OpenTitan’s security under strong attack models before deployment in servers and Chromebooks. The evaluation analysed OpenTitan’s core security properties and led to several hardening measures and tooling improvements that benefit future tape-outs and deployments.

Fortifying Cryptography with Impeccable Circuits: Impeccable Keccak Explained

Cybersecurity threats are evolving, and cryptographic implementations face growing risks from fault injection attacks. Fraunhofer AISEC’s research introduces Impeccable Keccak, a new approach to secure SPHINCS+, a post-quantum cryptography digital signature scheme that has been standardized by NIST in 2024. By leveraging impeccable circuits and ensuring active security, this represents a new approach to fault-resilient cryptography.